Conventionally, a DRAM (dynamic random access memory) performs writing in a cell capacitor through an NMOS or PMOS charge transfer gate. Therefore, when the cell transistor is driven between a power supply (V.sub.DD) and ground (GND), threshold voltage loss causes the high level, for example, bit "1" to be V.sub.DD -V.sub.TN for NMOS, or the low level, for example, bit "0" to be .vertline.V.sub.TP .vertline. for PMOS, both of which inhibit full rail writing of V.sub.DD -GND, where V.sub.TN and V.sub.TP are threshold voltages of NMOS and PMOS, respectively. Full rail writing can be usually performed by a word line boost. That is, the gate is driven to a voltage higher than (V.sub.DD +V.sub.TN) for the NMOS cell transistor, or to a voltage lower than (GND-V.sub.TP) for the PMOS cell transistor. Usually, this word line boost approach is widely used for NMOS.
U.S. Pat. No. 4,678,941 (Japanese Published Unexamined Patent Application No. 61-246994) discloses a word line clock circuit which negatively drives the word line in order to compensate for the threshold voltage loss in the PMOS cell transistor. However, when an NMOS transistor is used for the word line driver and the word line is boosted to a voltage lower than GND, there is a possibility that the junction between the substrate and a device region of the NMOS transistor will be forward biased thus giving rise to latch-up. Therefore, only a small amount of boost can essentially be allowed so as not to cause latch-up. To increase the boost, special considerations to prevent latch-up become necessary. Although the latch-up problem can be eliminated by using PMOS as the word line driver, PMOS is not desirable because it has a low driving capability at low voltages, and cannot access at high speed.
Japanese Published Unexamined Patent Application 57-18081 discloses a DRAM cell which increases the amount of signal charge stored in the cell capacitor by controlling the potential of an electrode of the cell capacitor. The cell capacitor is formed by a diffusion region of the cell transistor and a plate electrode provided on this diffusion region with an insulating layer therebetween. During writing, a voltage higher than full rail can be written by controlling the potential of the plate electrode. However, in DRAMs using a trench capacitor, the substrate is used as a capacitor electrode corresponding to the above-mentioned plate electrode. The substrate is usually connected to a reference voltage to maintain the threshold voltage of MOS transistors at constant, and to stabilize their operation. Therefore, the method of the above patent cannot be used for DRAMs using the trench capacitors.